Conventionally, in production of a silicon wafer used as a semiconductor substrate material, a semiconductor wafer is generally produced by growing a cylindrical semiconductor single crystal ingot by Czochralski (CZ) method, Floating Zone (FZ) method, and so forth, cutting (slicing) the grown semiconductor single crystal ingot into a thin plate to produce a wafer, and subsequently subjecting the obtained wafer to a chamfering process for chamfering a peripheral portion of the wafer to prevent breakage or crack of the wafer, a lapping process for adjusting a thickness and flatness of the wafer, an etching process for etching the wafer to remove mechanical damage on the wafer, a polishing process for further improving surface roughness and flatness of the etched wafer to be a mirror surface, and a cleaning process for removing polishing agent and dust particles adhered on the wafer. Main processes are described in these semiconductor wafer production processes. Other processes such as a heat treatment process can be added therein, and the order of the processes can be changed.
In recent years, with remarkably higher integration of a semiconductor device due to breakthrough in semiconductor device technology, a demand for quality on a semiconductor wafer to be a substrate for a semiconductor device has become more strictly. For example, in production of a semiconductor device, a process for forming resist patterns on the semiconductor wafer produced as described above using KrF excimer laser light (wavelength=0.248 μm) which is ultraviolet, or the like, as a light source is generally performed at about 20 times–30 times. Taking DRAM (dynamic random access memory) for an example, on 64 Mbit DRAM, which is currently mass-produced, resist patterns with 0.25 μm–0.20 μm are formed. As device patterns become finer accompanying high integration and high performance of a recent semiconductor integrated circuit as described above, further improvement of size accuracy and overlay accuracy of resist patterns has been desired, and demand for quality on a semiconductor wafer on which circuit patterns are formed has become more strictly.
For example, as device patterns become finer as described above, errors in device patterns occur in a photolithography process etc. even in the case where only extremely small waviness and so on exist on a semiconductor wafer, and therefore a problem that a yield of a semiconductor device decreases has occurred. On the other hand, in order to lower production cost by effective use of a semiconductor wafer, a flat semiconductor wafer up to the vicinity of a periphery of the wafer main surface (at the limit of the chamfered portion) has been desired so as to form a device on the wide area of the wafer.
As one of the important characteristics desired for such a semiconductor wafer to be a substrate for a semiconductor device, shape quality of a semiconductor wafer is mentioned. The shape quality of a semiconductor wafer generally includes various parameters such as diameter, thickness, parallelism, flatness, warpage, waviness called bow, warp, or the like, which is relatively long-period asperity or asperity having a period of several mm, and surface roughness. Recently, in such parameters concerning shape quality, there are many cases where a quality called global flatness of back surface reference or front surface reference, or site flatness of back surface reference or front surface reference is attached importance.
In particular, as an index of flatness, global flatness of back surface reference is called as GBIR (Global Back Ideal Range), and generally defined as a range of displacement between the maximum position and the minimum position to one reference plane being set in the wafer surface. It corresponds to TTV (total thickness variation) which is a conventional and usual specification.
Site flatness of back surface reference is called as SBIR (Site Back Ideal Range), and corresponds to LTV which was considerably frequently used in the past. When setting a back surface of a wafer as a reference plane, and further setting a plane including a site center point at each site as a focus plane, this SBIR is evaluated at each site as the sum of absolute values of maximum displacement values on + side and − side, respectively, from the focus plane in the site. Generally in the case of an 8-inch wafer (a diameter is 200 mm) and so forth, it is evaluated in an area of a site having a size of about 20×20 mm. The size of the site can be varied in accordance with a diameter of the wafer or a specification.
Besides, site flatness of surface reference is called as SFQR (Site Front Least Squares Range). When setting a plane in a site calculated by least squares of data in a determined site as a reference plane, it is evaluated at each site as the sum of absolute values of maximum displacement values on + side and − side, respectively, from the reference plane.
In addition, a quality called nanotopography is also attached importance. Nanotopography (occasionally referred to as nanotopology) is asperity having a wavelength of about 0.2 mm to 20 nm and amplitude of about several nm to 100 nm. As to a method of evaluating thereof, a vertical interval of the asperity on a wafer surface (PV value; peak to valley) is evaluated in a region of a square block area having a side of about 0.1 mm–10 mm or a circular block area having a diameter of about 0.1 mm to 10 mm (this area is called as WINDOW SIZE or the like). This PV value is occasionally referred to as Nanotopography Height, or the like. In evaluation of a semiconductor wafer using nanotopography, it is especially desired that the maximum of asperity existing on a wafer surface is small. Generally, a wafer is measured in multiple square block areas having a size of 2 mm×2 mm, and evaluated by the maximum of PV value thereof. As the maximum of the PV value is smaller, the wafer is evaluated as a more excellent wafer in quality. There is a case where shape quality of a wafer is evaluated by how much area of FQA (Fixed Quality Area) the region over tolerance occupies.
In the case of evaluating shape quality of a semiconductor wafer using the indexes as described above, if a design rule in device production processes was up to 0.18 μm, a semiconductor wafer having sufficient shape quality could be obtained when satisfying the rule. However, as the specification becomes stricter such that the design rule is up to 0.15 μm or further up to 0.13 μm due to recent higher integration of a semiconductor device, there are problems that resist patterns can not be precisely formed on even the semiconductor wafer which satisfies the aforementioned indexes when a device is actually formed on the wafer, and so on. This causes decrease of a yield.
Many treating apparatuses such as an aligner are used in the device production processes. With finer device patterns, compatibility between a chuck for holding a wafer used in each treating apparatus and a wafer shape has become a problem. As to such compatibility between the wafer chuck and the wafer shape, matching between a shape of the wafer chuck and waviness or a shape of a peripheral portion of the wafer is important. In particular, there are many cases that an inflection point where a rate of shape variation is large becomes a problem in the peripheral portion of the wafer. Therefore, there is a need to precisely comprehend a point where the wafer shape varies and a degree thereof.
Although it was possible to accurately evaluate flatness at the center of the wafer with the aforementioned indexes such as GBIR, SBIR and SFQR, it was impossible to accurately evaluate a shape in the peripheral portion of the wafer, in particular in the vicinity of an interface between a main surface of the wafer and a chamfering portion. Also in the case of nanotopography, it was impossible to perform a precise filtering due to no data outside an edge portion of the wafer, and therefore the peripheral portion of the wafer could not be accurately evaluated.
That is, it was impossible to precisely judge a semiconductor wafer preferable for use in a stepper (a common name of a step-type projection aligner) in which a wafer is repeatedly stepped and exposed to projection images of mask patterns (reticle patterns), a scanning-type aligner, and so forth, by use of indexes described above such as SFQR.
Accordingly, in order to precisely judge compatibility between the wafer chuck and the shape of the wafer etc. in each device process, in more detail, in each treating apparatus, an index has been needed, in which a shape of a peripheral portion of a wafer can be accurately evaluated and further shapes of a front surface and a back surface of a wafer can be separately evaluated.